Field of the Invention
The invention relates to a method for providing a macro placement of an integrated circuit (IC), and more particularly to a method for providing a macro placement of an IC with smoothness and dynamic macro channel.
Description of the Related Art
In recent years, the developing process of integrated circuits (ICs) such as super larger scale integrated circuits (LSIs) generally utilizes computer assisted design (CAD). According to such a developing process based on CAD, abstract circuit data, which corresponds to functions of an integrated circuit to be developed, is defined by using a so-called hardware description language (HDL), and the defined circuit is used to form a concrete circuit structure to be mounted on a chip.
Before the IC chips are manufactured (or implemented), the placements, the floor plans, and the layout areas of the IC chips are first considered so as to determine a die size for each IC chip. In general, the die size will affect the manufacturing cost of the IC chip. Therefore, it is desirable to optimize the floor plan of an IC chip for minimizing the layout area of the IC chip.